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this is information on a product in full production. september 2013 docid024020 rev 2 1/34 m24c01/02-w m24c01/02-r m24c02-f 1-kbit and 2-kbit serial i2c bus eeproms datasheet - production data 1. not recommended for new designs features ? compatible with all i 2 c bus modes: ? 400 khz ? 100 khz ? memory array: ? 1 kbit (128 bytes) of eeprom ? 2 kbit (256 bytes) of eeprom ? page size: 16 bytes ? single supply voltage: ? m24c01/02-w: 2.5 v to 5.5 v ? m24c01/02-r: 1.8 v to 5.5 v ? m24c02-f: 1.7 v to 5.5 v (full temperature range) and 1.6 v to 1.7 v (limited temperature range) ? write: ? byte write within 5 ms ? page write within 5 ms ? operating temperature range: from -40 c up to +85 c ? random and sequential read modes ? write protect of the whole memory array ? enhanced esd/latch-up protection ? more than 4 million write cycles ? more than 200-year data retention ? packages: ? rohs compliant and halogen-free (ecopack ? ) pdip8 (bn) (1) tssop8 (dw) 169 mil width ufdfpn8 (mc) so8 (mn) 150 mil width www.st.com
contents m24c01/02-w m24c01/02-r m24c02-f 2/34 docid024020 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 chip enable (e2, e1, e0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 write control (wc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 16 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
docid024020 rev 2 3/34 m24c01/02-w m24c01/02-r m24c02-f contents 3 6 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of tables m24c01/02-w m24c01/02-r m24c02-f 4/34 docid024020 rev 2 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. operating conditions (voltage range w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. operating conditions (voltage range r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. operating conditions (voltage range f, for de vices identified by process letter t) . . . . . . . 20 table 8. operating conditions (voltage ra nge f, for all other devices) . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 13. dc characteristics (m24c01/02-w, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. dc characteristics (m24c01/02-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 15. dc characteristics (m24c02-f, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 16. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 17. 100 khz ac characteristics (i 2 c standard mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 28 table 19. so8n ? 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 29 table 20. pdip8 ? 8-pin plastic dip, 0.25 mm lead fram e, package mechanical data. . . . . . . . . . . . 30 table 21. ufdfpn8 (mlp8) ? package dime nsions (ufdfpn: ult ra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
docid024020 rev 2 5/34 m24c01/02-w m24c01/02-r m24c02-f list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. write mode sequences with wc = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. write mode sequences with wc = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 8. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 29 figure 14. pdip8 ? 8-pin plastic dip, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 30 figure 15. ufdfpn8 (mlp8) ? package outline (ufdfpn: ultra thin fine pitch dual flat package, no lead) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
description m24c01/02-w m24c01/02-r m24c02-f 6/34 docid024020 rev 2 1 description the m24c01(c02) is a 1(2)-kbit i 2 c-compatible eeprom (electrically erasable programmable memory) organized as 128 (256) 8 bits. the m24c01/02-w can be accessed with a supply voltage from 2.5 v to 5.5 v, the m24c01/02-r can be accessed with a supply voltage from 1.8 v to 5.5 v, and the m24c02-f can be accessed either with a supply voltage from 1.7 v to 5.5 v (over the full temperature range) or with an extended supply voltage from 1.6 v to 1.7 v if the temperature is reduced to 0 c/ 85 c. all these devices operat e with a clock frequency of 400 khz. figure 1. logic diagram figure 2. 8-pin package connections, top view 2. see section 9: package mechanical data for package dimensions, and how to identify pin 1. table 1. signal names signal name function direction e2, e1, e0 chip enable input sda serial data i/o scl serial clock input wc write control input v cc supply voltage - v ss ground - ai01844f 3 e0-e2 sda v cc m24xxx wc scl v ss sda v ss scl wc e1 e0 v cc e2 ai01845f 1 2 3 4 8 7 6 5
docid024020 rev 2 7/34 m24c01/02-w m24c01/02-r m24c02-f signal description 33 2 signal description 2.1 serial clock (scl) the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be co nnected from serial data (sda) to v cc ( figure 10 indicates how to calculate the value of the pull-up resistor). 2.3 chip enable (e2, e1, e0) (e2,e1,e0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit devic e select code. these inputs must be tied to v cc or v ss , as shown in table 2: device select code . when not connected (l eft floating), these inputs are read as low (0). 2.4 write control (wc ) this input signal is useful for protecting the entire contents of the memory from inadvertent write operations. write operations are disa bled to the entire memory array when write control ( wc ) is driven high. write operations are enabled when write control ( wc ) is either driven low or left floating. when write control ( wc ) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. 2.5 v ss (ground) v ss is the reference for the v cc supply voltage.
signal description m24c01/02-w m24c01/02-r m24c02-f 8/34 docid024020 rev 2 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 8: dc and ac parameters ) . in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 2.6.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ) and the rise time must not vary faster than 1 v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 8: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 8: dc and ac parameters ). in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
docid024020 rev 2 9/34 m24c01/02-w m24c01/02-r m24c02-f memory organization 33 3 memory organization the memory is organized as shown below. figure 3. block diagram ms30996v1 wc control logic high voltage generator i/o shift register address register and counter data register 1 page x decoder y decoder e2, e1, e0 scl sda
device operation m24c01/02-w m24c01/02-r m24c02-f 10/34 docid024020 rev 2 4 device operation the device supports the i 2 c protocol. this is summarized in figure 4 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a dat a transfer can only be initia ted by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 4. i 2 c bus protocol scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
docid024020 rev 2 11/34 m24c01/02-w m24c01/02-r m24c02-f device operation 33 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is followed by noack can be fo llowed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
device operation m24c01/02-w m24c01/02-r m24c02-f 12/34 docid024020 rev 2 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start conditio n. following this, the bus master s ends the device select code, shown in table 2 (on serial data (sda), most significant bit first). the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the de vice does not match the device select code, it de selects itself from the bus, and goes into standby mode. table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address rw b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 e2 e1 e0 rw
docid024020 rev 2 13/34 m24c01/02-w m24c01/02-r m24c02-f instructions 33 5 instructions 5.1 write operations following a start condition the bus master sends a device select code with the r/ w bit (r w ) reset to 0. the device acknowledges this, as shown in figure 5 , and waits for the address byte. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is triggered. a stop condition at any othe r time slot does not trigger the internal write cycle. after the stop condition and the successful completion of an internal write cycle (t w ), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. if the write control input (wc) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in figure 6 . table 3. address byte a7 a6 a5 a4 a3 a2 a1 a0
instructions m24c01/02-w m24c01/02-r m24c02-f 14/34 docid024020 rev 2 5.1.1 byte write after the device select code and the address by te, the bus master sends one data byte. if the addressed location is write-protected, by write control ( wc ) being driven high, the device replies with noack, and the location is not modified. if, instead, the addressed location is not write-protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 5 . figure 5. write mode sequences with wc = 0 (data write enabled) stop start byte write dev select byte address data in wc start page write dev select byte address data in 1 data in 2 wc data in 3 ai02804c page write (cont'd) wc (cont'd) stop data in n ack r/w ack ack ack ack ack ack r/w ack ack
docid024020 rev 2 15/34 m24c01/02-w m24c01/02-r m24c02-f instructions 33 5.1.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a8/a4, ar e the same. if more bytes are se nt than will fit up to the end of the page, a ?roll-over? occurs, i.e. the by tes exceeding the page end are written on the same page, from location 0. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if write control ( wc ) is low. if write control ( wc ) is high, the contents of the addressed memory location are not modified, an d each data byte is followed by a noack, as shown in figure 6 . after each transferred byte, the internal page address counter is incremented. the transfer is terminated by the bu s master generating a stop condition. figure 6. write mode sequences with wc = 1 (data write inhibited) stop start byte write dev select byte address data in wc start page write dev select byte address data in 1 data in 2 wc data in 3 ai02803d page write (cont'd) wc (cont'd) stop data in n ack ack no ack r/w ack ack no ack no ack r/w no ack no ack
instructions m24c01/02-w m24c01/02-r m24c02-f 16/34 docid024020 rev 2 5.1.3 minimizing write delays by polling on ack the maximum write time (t w ) is shown in ac characteristics tables in section 8: dc and ac parameters , but the typical time is shorter. to ma ke use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 7 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 7. write cycle polling flowchart using ack write cycle in progress a i01847d ai01847e next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write cperation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no startcondition continue the write operation continue the random read operation
docid024020 rev 2 17/34 m24c01/02-w m24c01/02-r m24c02-f instructions 33 5.2 read operations read operations are performed independently of the state of the write control ( wc ) signal. after the successful completion of a read oper ation, the device internal address counter is incremented by one, to point to the next byte address. for the read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. if the bus master does not acknowledge during this 9th time, the device terminates t he data transfer and switches to its standby mode. figure 8. read mode sequences start dev select * byte address start dev select data out 1 ai01942b data out n stop start current address read dev select data out random address read stop start dev select * data out sequential current read stop data out n start dev select * byte address sequential random read start dev select * data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
initial delivery state m24c01/02-w m24c01/02-r m24c02-f 18/34 docid024020 rev 2 5.2.1 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 8 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the r w bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/ w bit set to 1. the device acknowledges this, and outputs the byte addressed by the inter nal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition , as shown in figure 8 , without acknowledging the byte. 5.2.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next by te in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 8 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 6 initial delivery state the device is delivered with all the memory ar ray bits set to 1 (each byte contains ffh).
docid024020 rev 2 19/34 m24c01/02-w m24c01/02-r m24c02-f maximum rating 33 7 maximum rating stressing the device outside the ratings listed in table 4 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature - 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for small b ody, sn-pb or pb-free assembly), the st ecopack? 7191395 specification, and the european directive on re strictions of hazardous substances (rohs) 2011/65/eu. c pdip-specific lead temperature during soldering - 260 (2) 2. t lead max must not be applied for more than 10 s. c i ol dc output current (sda = 0) - 5 ma v io input or output range ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v v esd electrostatic pulse (human body model) (3) 3. positive and negative pulses applied on different co mbinations of pin connections, according to aec- q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 ). - 3000 (4) 4. 4000 v for devices identified by process letters s or g. v
dc and ac parameters m24c01/02-w m24c01/02-r m24c02-f 20/34 docid024020 rev 2 8 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. table 5. operating conditions (voltage range w) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 400 khz table 6. operating conditions (voltage range r) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c f c operating clock frequency - 400 khz table 7. operating conditions (voltage range f, for devices identified by process letter t) symbol parameter min. max. u nit v cc supply voltage 1.60 1.65 1.70 5.5 v t a ambient operating temperature: read -40 -40 -40 85 c ambient operating temperature: write 0 -20 -40 85 f c operating clock frequency - - - 400 khz table 8. operating conditions (voltage range f, for all other devices) symbol parameter min. max. u nit v cc supply voltage 1.7 5.5 v t a ambient operating temperature -20 85 c f c operating clock frequency - 400 khz
docid024020 rev 2 21/34 m24c01/02-w m24c01/02-r m24c02-f dc and ac parameters 33 figure 9. ac measurement i/o waveform table 9. ac measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf scl input rise/fall time, sda input fall time - 50 ns input levels 0.2 v cc to 0.8 v cc v input and output timing reference levels 0.3 v cc to 0.7 v cc v table 10. input parameters symbol parameter (1) 1. characterized only, not tested in production. test condition min. max. unit c in input capacitance (sda) - - 8 pf c in input capacitance (other pins) - - 6 pf z l input impedance (wc ) v in < 0.3 v cc 15 70 k z h v in > 0.7 v cc 500 - k table 11. cycling performance symbol parameter test condition (1) 1. cycling performance for products identified by process letter t. max. unit ncycle write cycle endurance ta 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycle ta = 85 c, v cc (min) < v cc < v cc (max) 1,200,000 table 12. memory ce ll data retention parameter test condition min. unit data retention (1) 1. for products identified by process letter t. the dat a retention behavior is check ed in production, while the 200-year limit is defined from charac terization and qualification results. ta = 55 c 200 year ms19774v1 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input voltage levels
dc and ac parameters m24c01/02-w m24c01/02-r m24c02-f 22/34 docid024020 rev 2 table 13. dc characteristics (m24c01/02-w, device grade 6) symbol parameter test conditions (in addition to those in table 5 and table 9 ) min. max. unit i li input leakage current (scl, sda, e2, e1) v in = v ss or v cc , device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) v cc = 5.5 v, f c = 400 khz - 1 (1) 1. 2 ma for devices identified by process letter g or s. ma v cc = 2.5 v, f c = 400 khz - 1 ma i cc0 supply current (write) during t w , 2.5 v v cc 5.5 v - 0.5 (2) 2. for devices identified by proces s letter t, value averaged over t w , characterized only (not tested in production). ma i cc1 standby supply current device not selected (3) , v in = v ss or v cc , v cc = 2.5 v 3. the device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -2 (4) 4. 1 a for previous devices ident ified by process letters g or s. a device not selected (3) , v in = v ss or v cc , v cc = 5.5 v -3 (4) a v il input low voltage (scl, sda, wc ) - ?0.45 0.3 v cc v v ih input high voltage (scl, sda, wc) -0.7 v cc v cc +1 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v or i ol = 3 ma, v cc = 5.5 v -0.4v
docid024020 rev 2 23/34 m24c01/02-w m24c01/02-r m24c02-f dc and ac parameters 33 table 14. dc characteristics (m24c01/02-r, device grade 6) symbol parameter test conditions (1) (in addition to those in table 6 and table 9 ) 1. if the application uses the voltage range r device with 2.5 v v cc 5.5 v and -40 c < ta < +85 c, please refer to table 13 instead of this table. min. max. unit i li input leakage current (e2, e1, scl, sda) v in = v ss or v cc , device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) v cc = 1.8 v, f c = 400 khz - 0.8 ma i cc0 supply current (write) during t w , v cc 1.8v v cc < 2.5 v - 0.5 (2) 2. for devices identified by proce ss letter t, value averaged over t w , characterized only (not tested in production). ma i cc1 standby supply current device not selected (3) , v in = v ss or v cc , v cc = 1.8 v 3. the device is not selected after power-up, after a re ad instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -1a v il input low voltage (scl, sda, wc ) 2.5 v v cc ?0.45 0.3 v cc v v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) v cc < 2.5 v 0.75 v cc 6.5 v input high voltage (wc ) v cc < 2.5 v 0.75 v cc v cc + 0.6 v v ol output low voltage i ol = 0.7 ma, v cc = 1.8 v - 0.2 v
dc and ac parameters m24c01/02-w m24c01/02-r m24c02-f 24/34 docid024020 rev 2 table 15. dc characteristics (m24c02-f, device grade 6) symbol parameter test conditions (1) (in addition to those in table 7 , table 8 and table 9 ) 1. if the application uses the vo ltage range f device with 2.5 v v cc 5.5 v , please refer to table 13 instead of this table. min. max. unit i li input leakage current (e2,e1, scl, sda) v in = v ss or v cc , device in standby mode - 2a i lo output leakage current v out = v ss or v cc, sda in hi-z, - 2 a i cc supply current (read) v cc = 1.6 v (2) or 1.7 v, f c = 400 khz 2. 1.6 v for devices identi fied by process letter t. -0.8ma i cc0 supply current (write) during t w , v cc 1.8 v - 0.5 (3) 3. for devices identified by proce ss letter t, value averaged over t w , characterized only (not tested in production). ma i cc1 standby supply current device not selected (4) , v in = v ss or v cc , v cc 1.8 v 4. the device is not selected after power-up, after a re ad instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct decoding of a write instruction). -1a v il input low voltage (scl, sda, wc ) 2.5 v v cc ?0.45 0.3 v cc v v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage (scl, sda) v cc < 2.5 v 0.75 v cc 6.5 v input high voltage (wc ) v cc < 2.5 v 0.75 v cc v cc +0.6 v v ol output low voltage i ol = 0.7 ma, v cc 1.8 v - 0.2 v
docid024020 rev 2 25/34 m24c01/02-w m24c01/02-r m24c02-f dc and ac parameters 33 table 16. 400 khz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (1) 1. characterized only, not tested in production. t f sda (out) fall time 20 (2) 2. with c l = 10 pf. 300 ns t xh1xh2 t r input signal rise time (3) 3. there is no min. or max. values for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 300 ns when f c < 400 khz. (3) ns t xl1xl2 t f input signal fall time (3) (3) ns t dxcx t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (4) 4. the min value for t clqx (data out hold time) of the m24xxx devices offers a safe timing to bridge the undefined region of the falling edge scl. t dh data out hold time 100 - ns t clqv (5) 5. t clqv is the time (from the falling edge of scl) requi red by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that r bus c bus time constant is within the values specified in figure 10. t aa clock low to next data valid (access time) - 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t w t wr write time - 5 ms t ns (1) pulse width ignored (input filter on scl and sda) - single glitch - 100 ns
dc and ac parameters m24c01/02-w m24c01/02-r m24c02-f 26/34 docid024020 rev 2 table 17. 100 khz ac characteristics (i 2 c standard mode) (1) 1. values recommended by the i 2 c bus standard-mode specification for a robust design of the i 2 c bus application. note that the m24x xx devices decode correctly fast er timings as specified in table 16: 400 khz ac characteristics . symbol alt. parameter min. max. unit f c f scl clock frequency - 100 khz t chcl t high clock pulse width high 4 - s t clch t low clock pulse width low 4.7 - s t xh1xh2 t r input signal rise time - 1 s t xl1xl2 t f input signal fall time - 300 ns t ql1ql2 (2) 2. characterized only. t f sda fall time - 300 ns t dxcx t su:dat data in setup time 250 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (3) 3. to avoid spurious start and stop conditions, a minimum delay is plac ed between scl=1 and the falling or rising edge of sda. t dh data out hold time 200 - ns t clqv (4) 4. t clqv is the time (from the falling edge of scl) requ ired by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that rbus cbus time const ant is within the values specified in figure 10 . t aa clock low to next data valid (access time) - 3450 ns t chdl (5) 5. for a restart condition, or following a write cycle. t su:sta start condition setup time 4.7 - s t dlcl t hd:sta start condition hold time 4 - s t chdh t su:sto stop condition setup time 4 - s t dhdl t buf time between stop condition and next start condition 4.7 - s t w t wr write time - 5 ms t ns (2) pulse width ignored (input filter on scl and sda), single glitch - 100 ns
docid024020 rev 2 27/34 m24c01/02-w m24c01/02-r m24c02-f dc and ac parameters 33 figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 11. ac waveforms ai14796b 1 10 100 10 100 1000 bus line capacitor (pf) bus line pull-up resistor (k ) i2c bus master m24xxx r bus v cc c bus scl sda r bus c bus = 400 ns here r bus c bus = 120 ns 4 k 30 pf the r x c time constant must be below the 400 ns time constant line represented on the left. bus bus scl sda out scl sda in data valid tclqv tclqx tchdh stop condition tchdl start condition write cycle tw ai00795i data valid tql1ql2 sda in tchdl start condition tdxch tcldx sda input sda change tchdh tdhdl stop condition start condition txh1xh2 scl tchcl tdlcl tclch txh1xh2 txl1xl2 txl1xl2 wc twldl tdhwh tchcl
package mechanical data m24c01/02-w m24c01/02-r m24c02-f 28/34 docid024020 rev 2 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 12. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 18. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ. min. max. typ. min. max. a ? ? 1.200 ? ? 0.0472 a1 ? 0.050 0.150 ? 0.0020 0.0059 a2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b ? 0.190 0.300 ? 0.0075 0.0118 c ? 0.090 0.200 ? 0.0035 0.0079 cp ? ? 0.100 ? ? 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 ? ? 0.0256 ? ? e 6.400 6.200 6.600 0.2520 0.2441 0.2598 e1 4.400 4.300 4.500 0.1732 0.1693 0.1772 l 0.600 0.450 0.750 0.0236 0.0177 0.0295 l1 1.000 ? ? 0.0394 ? ? ? 0 8 ? 0 8
docid024020 rev 2 29/34 m24c01/02-w m24c01/02-r m24c02-f package mechanical data 33 figure 13. so8n ? 8-lead plastic small outli ne, 150 mils body width, package outline 1. drawing is not to scale. table 19. so8n ? 8-lead pl astic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a ? ? 1.750 ? ? 0.0689 a1 ? 0.100 0.250 ? 0.0039 0.0098 a2 ? 1.250 ? ? 0.0492 ? b ? 0.280 0.480 ? 0.0110 0.0189 c ? 0.170 0.230 ? 0.0067 0.0091 ccc ? ? 0.100 ? ? 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 ? ? 0.0500 ? ? h ? 0.250 0.500 ? 0.0098 0.0197 k ? 0 8 ? 0 8 l ? 0.400 1.270 ? 0.0157 0.0500 l1 1.040 ? ? 0.0409 ? ? so-a e1 8 ccc b e a d c 1 e h x 45 a2 k 0.25 mm l l1 a1 gauge plane
package mechanical data m24c01/02-w m24c01/02-r m24c02-f 30/34 docid024020 rev 2 figure 14. pdip8 ? 8-pin plastic dip, 0.25 mm lead frame, package outline 1. drawing is not to scale. 2. not recommended for new designs. table 20. pdip8 ? 8-pin plastic dip, 0.25 mm lead frame, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ. min. max. typ. min. max. a ? ? 5.33 ? ? 0.2098 a1 ? 0.38 ? ? 0.0150 ? a2 3.30 2.92 4.95 0.1299 0.1150 0.1949 b 0.46 0.36 0.56 0.0181 0.0142 0.0220 b2 1.52 1.14 1.78 0.0598 0.0449 0.0701 c 0.25 0.20 0.36 0.0098 0.0079 0.0142 d 9.27 9.02 10.16 0.3650 0.3551 0.4000 e 7.87 7.62 8.26 0.3098 0.3000 0.3252 e1 6.35 6.10 7.11 0.2500 0.2402 0.2799 e 2.54 ? ? 0.1000 ? ? ea 7.62 ? ? 0.3000 ? ? eb ? ? 10.92 ? ? 0.4299 l 3.30 2.92 3.81 0.1299 0.1150 0.1500 pdip-b a2 a1 a l be d e1 8 1 c ea b2 eb e
docid024020 rev 2 31/34 m24c01/02-w m24c01/02-r m24c02-f package mechanical data 33 figure 15. ufdfpn8 (mlp8) ? package outline (ufdfpn: ultra thin fine pitch dual flat package, no lead) 1. drawing is not to scale. 2. the central pad (area e2 by d2 in the above illustration) is internally pulled to v ss . it must not be connected to any other voltage or signal line on the pcb, for example during the soldering process. table 21. ufdfpn8 (mlp8) ? package dimensions (ufdfpn: ultra thin fine pitch dual flat package, no lead) symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 (rev mc) ? 1.200 1.600 ? 0.0472 0.0630 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 (rev mc) ? 1.200 1.600 ? 0.0472 0.0630 e 0.500 ? ? 0.0197 ? ? k (rev mc) ? 0.300 ? ? 0.0118 ? l ? 0.300 0.500 ? 0.0118 0.0197 l1 ? ? 0.150 ? ? 0.0059 l3 ? 0.300 ? ? 0.0118 ? eee (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. ? 0.080 ? ? 0.0031 ? d e zw_meev2 a a1 eee l1 e b d2 l e2 l3 pin 1 k mc
part numbering m24c01/02-w m24c01/02-r m24c02-f 32/34 docid024020 rev 2 10 part numbering table 22. ordering information scheme example: m24c02 w mc 6 t p device type m24 = i 2 c serial access eeprom device function c01 = 1 kbit (128 x 8 bit) c02 = 2 kbit (256 x 8 bit) operating voltage w = v cc = 2.5 v to 5.5 v r = v cc = 1.8 v to 5.5 v f = v cc = 1.6 v or 1.7 v to 5.5 v package bn = pdip8 (1)(2) 1. rohs-compliant (ecopack1?) 2. not recommended for new designs. mn = so8 (150 mil width) (3) 3. rohs-compliant and halogen-free (ecopack2 ? ) dw = tssop8 (169 mil width) (3) mc = ufdfpn8 (mlp8) (3) device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option blank = standard packing t = tape and reel packing plating technology p or g = ecopack ? (rohs compliant)
docid024020 rev 2 33/34 m24c01/02-w m24c01/02-r m24c02-f revision history 33 11 revision history table 23. document revision history date revision changes 17-dec-2012 1 new m24c01/02 datasheet resulting from splitting the previous datasheet M24C08-x m24c04-x m24c02-x m24c01-x (revision 18) into separate datasheets. added part number m24c02-f. updated esd value in table 4 . updated standby supply current values (i cci ) in table 13 , table 14 and table 15 . 24-sep-2013 2 added: ? table 11: cycling performance ? table 7: operating conditions (voltage range f, for devices identified by process letter t) and table 8: operating conditions (voltage range f, for all other devices) updated: ? features : supply voltage, write cycles and data retention ? section 1: description ? note (1) under table 4: absolute maximum ratings ? table 12: memory cell data retention , table 13: dc characteristics (m24c01/02-w, device grade 6) , table 14: dc characteristics (m24c01/02-r, device grade 6) , table 15: dc characteristics (m24c02-f, device grade 6) , table 22: ordering information scheme ? figure 11: ac waveforms renamed figure 15 and table 21 .
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